I bought old (and cheap) Pentium-II 233 MHz machine from my employee. I found that it will officially support max. P2-333 MHz processors with 66 MHz FSB and 5x multiplier. However, I had spare Celeron-A 400 MHz (using slot-1 adapter) and decided to give it a try. Whoa and it booted @ 400 MHz! Jumpers must be set to 2-3/5-6, 2-3/5-6, 2-3/5-6 (A, B ,C) for 400 MHz. I think Celeron-A uses 6x multiplier when multiplier is se to 3.5x on mobo. I have no idea if voltages are suitable, but who cares, it works. Bios will complain about missing L2 cahce - it will not recognize L2 cache of Celeron and that's why I am writing this page. BIOS upgrade won't help - actually too new BIOS will not work at all. You must have 1.00.05.DT0 BIOS. Intel must have decided that you must by new board for celerons and added checks for Celeron not to work?!
Well ok, you got your Celeron on board and booting OS. BIOS will compain about missing L2 cache and sure you are missing it, resulting very slow system. You must enable L2 cache. I found that PowerLeap have some kind of CPU adapter, which suffers from same kind of problem. They have made patch for Linux kernel for enabling L2 cache. You can download it here (there are also CPU Control Panel for Windows, which allows to enable L2 cache). Below actual patch:
*** setup.c Tue Jan 25 16:51:19 2000
--- setup.c Tue Jan 25 17:01:13 2000
***************
*** 769,774 ****
--- 769,799 ----
if (c->cpuid_level > 0 && c->x86_vendor == X86_VENDOR_INTEL)
{
+
+ /* l2 hack to enable L2 cache on Celeron pschneid 21.1.2000 */
+
+ printk ("Attempt to enable L2 cache on a Celeron\n");
+ __asm__ ("cli");
+ __asm__ ("wbinvd");
+ __asm__ ("movl %cr0,%eax");
+ __asm__ ("orl $0x40000000,%eax");
+ __asm__ ("movl %eax,%cr0");
+ __asm__ ("wbinvd");
+ __asm__ ("mov $0x11E, %ecx");
+ __asm__ ("rdmsr");
+ __asm__ ("or $0x00040101, %eax");
+ __asm__ ("mov $0x11E, %ecx");
+ __asm__ ("wrmsr");
+ __asm__ ("wbinvd");
+ __asm__ ("movl %cr0, %eax");
+ __asm__ ("andl $0xbfffffff, %eax");
+ __asm__ ("movl %eax, %cr0");
+ __asm__ ("wbinvd");
+ __asm__ ("sti");
+ printk ("Survived so far...\n");
+
+ /* end of l2 hack */
+
if(c->x86_capability&(1<<18))
{
/* Disable processor serial number on Intel Pentium III
/* END
|
However, this patch will not apply nicely to 2.6.x series of kernel. I
will explain what you have to do to apply this patch to 2.6.x kernel. First,
open file arch/i386/kernel/cpu/intel.c. It contains Intel
intialization code. Then find function init_intel and
string CONFIG_X_6_F00F_BUG. Below it, you have this kind of structure:
select_idle_routine(c);
if (c->cpuid_level > 1) {
/* supports eax=2 call */
int i, j, n;
int regs[4];
unsigned char *dp = (unsigned char *)regs;
Add patch after those lines. Add only printk and __asm__ lines and modify printk to print KERN_NOTICE device:
/* l2 hack to enable L2 cache on Celeron pschneid 21.1.2000 */
/* For 2.6.x by Jari Eskelinen |
Compile and install. You should now have full 128kB L2 cache:
jarpatus@ghoul:~$ dmesg |grep "CPU: L" CPU: L1 I cache: 16K, L1 D cache: 16K CPU: L2 cache: 128K jarpatus@ghoul:~$ cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 6 model name : Celeron (Mendocino) stepping : 5 cpu MHz : 398.925 cache size : 128 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 2 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 mmx fxsr bogomips : 786.43 |
Enjoy. In case of problems, I probably can't help since I have no understanding about assembly code written by PowerLeap. I can try however so drop E-Mail if you want.